1. Field of the Invention
The present invention relates to a method of arranging components in a semiconductor device on a substrate. More precisely, it relates to a method of arranging components so that a wiring capacitance (network capacitance) of conductors connecting associated components in a specific network is lower than a predetermined value.
In a logic design of an LSI, such as a gate array, the wiring capacitance of a specific network having a high frequency or a large number of fan-outs must be carefully taken into account, and accordingly, the arrangement or location of components constituting the specific network must be carefully taken into consideration so as to satisfy the wiring capacitance of the components.
The term "component" is used as a generic term in this specification and covers various logic circuits, semiconductor elements, flip-flops, gate elements, etc.
2. Description of the Related Art
There are two known arrangements of components in a semiconductor device, such as a CMOS gate array. According to a first known arrangement algorithm, a designer designates the arrangement of the cells without considering the wiring capacitance of the specific network, so that the wiring, i.e., the conductor arrangement of the connection of the components, can be automatically determined by a computer. On the other hand, in a second known algorithm arrangement, the arrangement and the electrical connection of the components are automatically determined by a computer, and thereafter, the wiring capacitance is computed to adjust the arrangement of the components and the wiring so that the wiring capacitance cannot exceed a predetermined value.
In the first mentioned arrangement, however, since the wiring capacitance in the specific network is not taken into account, the path of the conductors depends on the conductor arrangement of the circumferential components, and this results in a difficulty in obtaining a desired wiring capacitance by a designer. As a result, an electrical defect, such as electromigration, may occur.
In the latter arrangement, the arrangements of the components and the wiring must be manually modified, but this is troublesome and time-consuming.
The primary object of the present invention is to provide a method of arranging components in a semiconductor device in such a way that no rearrangement of the components and no rewiring are necessary, and by which the component arrangement can be determined and the wiring can be effectively conducted so as not to exceed a designer's intended wiring capacitance.